1. Field of the Invention
The present invention relates generally, as is indicated, to a semiconductor memory and more particularly to an electrically erasable programmable read-only memory (EEPROM). Even more particularly, the present invention relates to a flash-type EEPROM which is a block-erasure-type EEPROM.
2. Description of the Prior Art
Generally, the design of flash-type EEPROMs, is based on that of EEPROMs. Therefore, the contents of flash-type EEPROMs can be written in and erased electrically. In flash-type EEPROMs in particular, erasure can be achieved only as a chip or in units of blocks.
According to the prior art, to test the operation of each block in a semiconductor memory formed from a flash-type EEPROM, a "0" initially is written to all memory cells. Thereafter, the blocks whose contents are to be erased are selected one by one, so as to perform an erasure operation test on a block-by-block basis while checking that the blocks whose contents are to be erased do not interfere with other blocks.
However, in the above prior art semiconductor memory formed from a flash-type EEPROM, it takes about one second to erase the contents of one block regardless of the size of the block. As is noted above, the blocks whose contents are to be erased are selected one by one for an erasure operation test. Therefore, if the semiconductor memory has N blocks, it takes about N.times.1 seconds to complete the erasure operation test of all the blocks. As a result, in the case of a semiconductor memory having a 1-megabit storage capacity with a 4-kilobyte block size, the erasure operation test takes as long as 32 seconds. This presents the problem that the cost of an erasure operation test, at least with respect to time, is extremely high.
Accordingly, there is a strong need in the art for a semiconductor memory that can be tested for erasure operation in a shorter time and, therefore, can reduce the cost associated with an erasure operation test.
The present invention overcomes the aforementioned and other shortcomings of the above known and similar semiconductor memories. The present invention is summarized and described in detail below.